In general, semiconductor memory products such as an SRAM and DRAM have sense amplifier circuits that amplify a small potential difference outputted to a pair of bit lines from a memory cell selected by inputting an external address signal during reading. Further, the semiconductor memory products have control circuits for starting the sense amplifier circuits with optimum timing. In recent years, low power consumption, high speed, and a small area have been demanded of these circuits.
The following will describe a technique for a sense amplifier circuit of a known semiconductor integrated circuit and a technique of starting the sense amplifier circuit with optimum timing.
[First Known Technique]
First, the following will discuss a technique for a sense amplifier circuit of a known semiconductor integrated circuit. The first known technique is a sense amplifier circuit described in “CMOS VLSI DESIGN”, supervised by Takuo Sugano, edited by Tetsuya Iizuka, first edition, fourth reprint, Sep. 30, 1992, published by BAIFUKAN Co., LTD, pp. 186–189. This book shows a variety of sense amplifier circuits generally used in a DRAM, SRAM, and so on.
A first example is a latch sense amplifier (shown in FIG. 5.35(a) on p. 187 of the book). The latch sense amplifier is constituted of a latch circuit of two inverters connected to a pair of bit lines. The source terminals or drain terminals of the inverters are connected to each other and are fed with a control signal for starting the sense amplifier. When the pair of bit lines has a small potential difference, the sense amplifier is started to amplify the potential difference. After amplification is completed, the bit lines are amplified to a power supply level and a GND level, respectively. Thus, no DC current path is generated in the circuit. With this configuration, the latch sense amplifier has very low power consumption.
A second example is a current mirror sense amplifier (shown in FIG. 5.36(a) on p. 188 of the book). The current mirror sense amplifier amplifies a pair of bit lines by means of a load device using a current mirror. However, as shown in the figure, a current mirror sense amplifier circuit may be increased in offset voltage due to poor symmetry and thus interfere with speedup. Further, since the current mirror sense amplifier has a small output amplitude, for example, as shown in FIG. 5.36(b) on p. 188 of the book, further amplification has to be performed in the subsequent stage of the sense amplifier circuit. In general, current mirror sense amplifiers can offer enhanced speed. However, unlike the latch sense amplifier, the current mirror sense amplifier has large power consumption because a DC current path is present in the circuit even after the completion of amplification. Since the circuit is configured using the current mirror, the circuit is unsuitable to operations performed at low power supply voltages. Further, the current mirror sense amplifier requires a control signal for starting the sense amplifier circuit as in the case of the latch sense amplifier.
A third example is a single-ended sense amplifier (shown in FIG. 5.39 on p. 189 of the book). The single-ended sense amplifier has an extremely simple configuration in which a bit line is directly inputted to an inverter. Unlike the latch sense amplifier and the current mirror sense amplifier, the single-ended sense amplifier requires no control signal for starting a sense amplifier circuit. However, the operating speed is determined by a threshold voltage (switching voltage) of the inverter. Thus, for example, when the bit line has a large load and a low amplitude velocity, amplification is not performed unless the potential of the bit line is reduced (or increased) to the threshold voltage of the inverter, resulting in a disadvantage in speedup. Moreover, when the bit line has a low amplitude velocity as described above, flow-through current is applied between the power supply of the inverter and GND, resulting in large power consumption.
[Second Known Technique]
The following will describe a known circuit technique for optimizing the start timing of a sense amplifier circuit of a semiconductor integrated circuit.
As described in the explanation of the known latch sense amplifier and current mirror sense amplifier, a sense amplifier circuit generally requires a control signal for starting the sense amplifier. Further, the sense amplifier can be started only after a potential difference of a pair of signal lines inputted to the sense amplifier circuit reaches a certain value or higher (for example, a potential difference not less than 100 mV, which is determined in consideration of the unbalanced characteristics of devices constituting the sense amplifier circuit and an offset voltage generated by the influence of coupling noise on the pair of signal lines, and a malfunction may occur unless the sense amplifier circuit is started with the potential difference or higher). Thus, a circuit is necessary for accurately detecting a potential difference of the pair of signal lines. Alternatively, the following circuit needs to be devised: in consideration of the load and driving capability of the pair of signal lines, a delay circuit or the like previously sets timing at which the pair of signal lines has a potential difference of the certain value or higher, and the start signal of the sense amplifier circuit is generated.
The second known technique of the semiconductor memory having a unit for dealing with the above problem includes a semiconductor memory disclosed in JP-A-9-259589. The semiconductor memory disclosed in JP-A-9-259589 will be simply discussed below. Some drawings and sentences are cited from the publication of unexamined application. FIG. 9 is a diagram showing the configuration of the semiconductor memory.
In FIG. 9, bit lines BL and BR are arranged longitudinally, word lines (W1 to Wn) are arranged laterally, and a plurality of memory cells (MC1 to MCn) are arranged respectively on the intersections of the bit lines and the word lines. Further, dummy bit lines DBL and DBR are arranged longitudinally. Dummy memory cells (MD1 to MDn), which are identical to the memory cells (MC1 to MCn) in structure and size, are arranged respectively on the intersections of the dummy bit lines DBL and DBR and the word lines (W1 to Wn). Moreover, the dummy bit lines DBL and DBR are inputted to a dummy sense amplifier DSA. The dummy sense amplifier outputs a signal SAD. An inverter INV is fed with the signal SAD and outputs a sense amplifier activating signal SC.
The effect of the configuration will be briefly discussed below. In addition to the normal memory cells (MC1 to MCn), the dummy memory cells (MD1 to MDn) are provided which are identical in structure to the normal memory cells, and the dummy bit lines DBL and DBR are provided which are equal in load to the normal bit lines BL and BR, so that the delay time of the normal bit lines BL and BR and the delay time of the dummy bit lines DBL and DBR can be compensated to an equal value. Thus, during reading, it is possible to generate start timing most suitable for the sense amplifier circuit based on the signals of the dummy bit lines DBL and DBR connected to the dummy memory cells (MD1 to MDn).
FIG. 9 shows a so-called replica circuit. A number of various configurations are proposed in addition to the above configuration.
However, the configurations of the first known technique and the second known technique have the following problems:
As described above, in the sense amplifier circuit discussed in the book, the latch sense amplifier and the current mirror sense amplifier require a control signal for starting the sense amplifier circuit. Hence, another circuit is necessary for generating the start timing of the sense amplifier circuit, thereby increasing a circuit area. Further, in actual memory products, all memory cells are not identical in characteristics and capability due to processing variations and so on in a semiconductor manufacturing process. Thus, a pair of bit lines (a pair of signal lines) does not have constant amplitude time. For this reason, it is normally necessary to generate the start timing of the sense amplifier circuit in synchronization with the timing of reading data from a memory cell having the lowest capability. Hence, the circuit is designed with an excessive timing margin for the start timing of the sense amplifier circuit, thereby interfering with speedup. The single-ended sense amplifier does not require a control signal for starting the sense amplifier circuit. However, as described above, when the bit line has slow transition speed, the single-ended sense amplifier is disadvantageous in speedup and flow-through current is applied between the power supply of the inverter and GND, resulting in large power consumption.
The configuration using the replica circuit disclosed in JP-A-9-259589 can generate start timing most suitable for the sense amplifier circuit. However, in general, the replica circuit additionally requires dummy memory cells other than memory cells and requires a control circuit or the like for generating the start timing of the sense amplifier circuit in response to a signal from the dummy bit line, thereby increasing a circuit area. Further, in actual memory products, all memory cells are not identical in characteristics due to processing variations and so on in a semiconductor manufacturing process. Thus, normally memory cells and dummy memory cells are not identical in characteristics and thus a pair of bit lines and a pair of dummy bit lines do not have constant amplitude time. For this reason, it is generally necessary to generate the start timing of the sense amplifier circuit in synchronization with the timing of reading data from a memory cell having the lowest capability. Hence, the circuit is designed with an excessive timing margin for the start timing of the sense amplifier circuit, thereby interfering with speedup.